DRV 2009 - Call for Participation

CALL FOR PARTICIPATION

Scope -- Venue -- Workshop Registration -- Advance Program -- Additional Information -- Committees

Scope

As silicon based CMOS technologies are fast approaching their ultimate limits, reliability is threatened by issues such as process, voltage and temperature variability, accelerated aging and wearout, radiation induced soft-errors and cross talk. In particular, variability of process, voltage and temperature represent a significant threat not only for parametric yield but also for reliability, since they induce timing faults that are extremely difficult to detect during manufacturing testing. It results on increasing ratio of circuits passing fabrication test that are susceptible to manifest failures in the field.

These problems are creating barriers to further technology scaling and are forcing the introduction of new process, design and test solutions aimed at maintaining acceptable levels of reliability.

As elimination of these issues is becoming increasingly difficult, various design techniques are emerging to circumvent them. These techniques may incur area, power, yield or performance penalties. Thus, to enable their adoption by the industry there is need for novel solutions to minimize penalties and provide automation tools.

The goal of this workshop is to create an informal forum to discuss those design, EDA and test innovations enabling chips to maintain acceptable reliability levels at reasonable cost.

Representative topics include, but are not limited to:

Reliability issues in advanced CMOS
Variability-aware design
Radiation effects in advanced CMOS
Design for reliability in advanced CMOS
Fault tolerant architectures
Variability mitigation
Self-calibrating architectures
On-line monitoring of circuit parameters
Design automation for self-calibrating and fault tolerant architectures
Variability insensitive architectures
Reliability assessment tools

The Venue

top

DRV 2009 will be held at the Austin Convention Center, Austin, Texas. Austin is the capital of the state of Texas, and its 1888 capitol building is an interesting landmark. Also of interest are the main campus of The University of Texas and the Lyndon B. Johnson Library and Museum. Close to the convention center is the lively East Sixth Street entertainment district which features many restaurants and a variety of music in the Live Music Capital of the World. The downtown area has miles of waterfront trails suitable for walking and jogging and is also home to the largest urban bat population in the US whose spectacular flight can be observed just before sunset. For more information about Austin, visit http://www.austintexas.org. Lodging for DRV 2009 is in several hotels in the vicinity of the convention center.

Reserve a hotel room online or call 1.800.262.9974 or 404.842.0000.

Workshop Registration

top

All Test Week activities require a registration badge for admittance. You can register online and get an early registration discount or on-site at regular rates during Test Week at the ITC registration counter in the Austin Convention Center. See page 28 of the Advance Program for further details and registration hours. Registration will begin Sunday morning at 7:30 am.

Advance Program

top

Thursday -- Friday

November 05, 2009 (Thursday)

4:00 PM - 5:15 PM	OPENING SESSION
	Opening Remarks General Co-Chairs: Michael Nicolaidis, TIMA & Yervant Zorian, Virage Logic Program Co-Chairs: Adit Singh, Auburn University & Sreejit Chakravarty, LSI
	Thursday Keynote: Effects Of Charge-Sharing On SER For Advanced Technology Nodes Prof. Bharat Bhuva, Vanderbilt University

5:15 PM - 6:15 PM	Session 1
	Statistical Memory Analysis for Robust SRAM Design Miguel Miranda, Paul Zuber, Petr Dobrolvolny, IMEC Labs, Belgium
	Alpha-induced SEU Sensitivity Dependencies on Logic Cells Layout Configurations P. Rech¹, A. Paccagnella¹, P. Bernardi², M. Grosso², M. Sonza Reorda², F. Melchiori³ and D. Appello³ ¹ Universita’ di Padova, ² Politecnico di Torino, ³ STMicroelectronics, Italy

7:00 PM - 9:00 PM WORKSHOP RECEPTION

Friday 06, 2009 (Friday)

8:00 AM - 9:00 AM	Friday Keynote I: Statistical Design on the Verge of Maturity: Revisiting the Foundation Prof. Michael Orshansky, UT Austin

9:00 AM - 10:00 AM	Session 2
	Energy and Variability Aware Scheduling for Clusterized MpSoC Architecture Gilles Bizot, Nacer-Eddine Zergainoh and Michael Nicolaidis, TIMA France
	Effects of Power Consumption and Temperature on Lifetime Reliability of ArchC Based Processor Architecture Tushar Gupta, Clement Bertolini, Olivier Heron, Nicolas Ventroux, Thomas Zimmer, CEA France

10:00 AM - 10:30 AM COFFEE BREAK

10:30 AM - 11:30 AM	Friday Keynote II Dr. Magdy Abadir, Freescale

11:30 AM - 12:00 PM	Session 3
0:00 - 0:00	Realistic Timing Simulation Corners Combining Process, Voltage, Temperature (PVT) and Aging Variations for Automotive Designs Amr Haggag, Eric Verrett, Erwin Prinz, Norbet Huemmer Freescale Semiconductor, USA Francesco Gattel, Anna Cascella, Fausto Piazza, Vincent Huard, Emmanuel Vincent, David Souil, Sylvie Bruyere, Davide Appello STMicroelectronics, Italy, Numonyx, Italy, **STMicroelectronics, France

12:00 Noon - 1:00 PM LUNCH

1:00 PM - 2:30 PM	Session 4
	A SEU-Avoidance Method in Placement and Routing of SRAM-based FPGAs to Mitigate Soft Error Effects Somayeh Bahramnejad, Hamid R. Zarandi, Amirkabir University of Technology, Iran
	Post Manufacture CMOS Performance Tuning in the Presence of High Random Variability Adit Singh, Ahmed Faraz, Kautalya Mishra, Abhijit Chatterjee* Auburn University, USA *Georgia Institute of Technology, USA

2:30 PM - 4:00 PM	Panel Discussion: Design For Reliability: Too Many Ideas, Too Few Tools Moderater: TBD
	Panelists: Dr. S. Patil, Intel Dr. A. Majumder, AMD Prof. M. Orshansky, UT Austin Xinli Gu, CISCO Systems Rob Aitken, ARM Prof. A. Chatterjee, Georgia Tech.

Additional Information

top

Michael Nicolaidis, TIMA Laboratory	Yervant Zorian, Virage Logic
Tel: +33476575060 Fax: +33 4 76 57 49 81 Email: michael.nicolaidis@imag.fr	Tel: +1 (510) 360-8035 Fax: +1 (510) 360-8078 yervant.zorian@viragelogic.com

Committees

top

General Chairs
Michael Nicolaidis, TIMA
Yervant Zorian, Virage Logic

Vice General Chair
Rajesh Galivanche, Intel
Lorena Anghel, TIMA

Program Chairs
Adit Singh, Auburn U.
Sreejit Chakravarty, LSI

Vice Program Chairs
TBD

Finance Chair:
Dimitris Gizopoulos, Pireaus U.

Publicity Chair:
Yiorgos Makris , Yale University

Panels Chair
Subhasish Mitra, Stanford U.

Publications Chair:
Saibal Mukhopadhyay, GaTech

For more information, visit us on the web at: http://www.itctestweek.org

The 2nd IEEE Workshop on Design for Reliability and Variability (DRV 2009) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).